1. Field of the Invention
This invention relates generally to semiconductor memory units and, more particularly, to semiconductor memory unit in which a built-in-self-test unit has been incorporated.
2. Description of the Related Art
As the number of storage cells and the complexity of semiconductor memories have increased, the length of time required to test the memories, not-with-standing decreasing clock cycle time, has continually increased. Originally, the semiconductor memory devices could be tested by coupling the devices to a testing unit. However, as the length of time has required to test each devices has increased, the use of testing units has become impractical and indeed provides a potential bottleneck the delivery of the devices to the marketplace.
The potential testing bottleneck has been resolved by providing incorporating apparatus internal to the device which can test the device with little external assistance. One implementation of self-testing apparatus is referred to as a built-in-self-test (BIST) unit. The BIST unit can test the storage cell array and associated equipment while coupled to a relatively simple test board. Using the BIST apparatus, one test board can control the testing procedures of a multiplicity of memory units. Typically, the result of the memory unit test by the BIST unit is communicated through a single memory unit terminal.
The BIST unit, in response to commands from the associated test board, typically tests the entire storage cell and provides an indicia of the results of the test procedure. In many situations, limiting the test procedures to those involving the entire memory unit can result in an unsatisfactory test procedure. For example, in testing a prototype memory unit, the failure of the prototype memory unit may be the result of either a failure of the BIST unit or a design flaw in a portion of the memory unit. In either situation, the mere failure of the test procedure does not provide enough information to localize problem with sufficient accuracy to know how to eliminate the problem.
One approach to the problem of limiting the portion of the memory unit being tested by the BIST unit is control the upper limit of the storage cell array addresses being tested. In this approach, by varying the address upper limit, the testing of the storage cell array can be systematically expanded to include the entire storage cell array. However, this test procedure is not useful for any address above that address including the first-identified defect. And this approach is particularly unsatisfactory when the identified defect occurs at a relatively low address.
A need has therefore been felt for a built-in-test-unit (BIST) unit and associated procedures which would permit the testing of a selected portion of the memory unit and the communication of the results of this partial memory unit test. In addition, it is desirable that this increased functionality of the BIST unit be accomplished without the requiring additional terminals for the memory unit.